Gate structure for semiconductor devices

ABSTRACT

A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. patentapplication Ser. No. 16/870,087, filed May 8, 2020 and titled “GateStructure for Semiconductor Devices,” which is incorporated herein byreference in its entirety.

BACKGROUND

Integrated circuits have been widely used for various kinds ofapplications, and the demand for faster processing speed and lower powerconsumption is increasing. However, gate resistance highly influencesthe performance of the integrated circuit. Thus, optimization of theintegrated circuit layout design including various layers of features,such as conductive structures of vias coupled to the gate structures andother metal routing, is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A is an equivalent circuit of part of an integrated circuit, inaccordance with various embodiments.

FIG. 1B is a detailed circuit corresponding to the equivalent circuit ofpart of the integrated circuit in FIG. 1A, in accordance with variousembodiments.

FIG. 2A is a layout diagram in a plan view of part of the integratedcircuit corresponding to a part of FIG. 1B, in accordance with variousembodiments.

FIG. 2B is a cross-sectional view of part of the integrated circuit inFIG. 2A, in accordance with various embodiments.

FIG. 3 is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 1B, in accordancewith various embodiments.

FIG. 4A is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 1B, in accordancewith various embodiments.

FIG. 4B is a cross-sectional view of part of the integrated circuit inFIG. 4A, in accordance with various embodiments.

FIG. 5A is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 1B, in accordancewith various embodiments.

FIG. 5B is a cross-sectional view of part of the integrated circuit inFIG. 5A, in accordance with various embodiments.

FIG. 6A is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 1B, in accordancewith various embodiments.

FIG. 6B is a cross-sectional view of part of the integrated circuit inFIG. 6A, in accordance with various embodiments.

FIG. 7A is an equivalent circuit of part of an integrated circuit, inaccordance with various embodiments.

FIG. 7B is a detailed circuit corresponding to the equivalent circuit ofpart of the integrated circuit in FIG. 7A, in accordance with variousembodiments.

FIG. 8A is a layout diagram in the plan view of part of the integratedcircuit corresponding to a part of FIG. 7B, in accordance with variousembodiments.

FIG. 8B is a cross-sectional view of part of the integrated circuit inFIG. 8A, in accordance with various embodiments.

FIG. 9A is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 7B, in accordancewith various embodiments.

FIG. 9B is a cross-sectional view of part of the integrated circuit inFIG. 9A, in accordance with various embodiments.

FIG. 10A is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 7B, in accordancewith various embodiments.

FIG. 10B is a cross-sectional view of part of the integrated circuit inFIG. 10A, in accordance with various embodiments.

FIG. 11 is another layout diagram in the plan view of part of theintegrated circuit corresponding to a part of FIG. 7B, in accordancewith various embodiments.

FIG. 12 is a flow chart of a method of fabricating the integratedcircuit, in accordance with some embodiments of the present disclosure.

FIG. 13 illustrates a comparison table of a gate resistance, inaccordance with some embodiments of the present disclosure.

FIG. 14 is a block diagram of a system for designing the integratedcircuit layout design, in accordance with some embodiments of thepresent disclosure.

FIG. 15 is a block diagram of an integrated circuit manufacturingsystem, and an integrated circuit manufacturing flow associatedtherewith, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinarymeanings in the art and in the specific context where each term is used.The use of examples in this specification, including examples of anyterms discussed herein, is illustrative only, and in no way limits thescope and meaning of the disclosure or of any exemplified term.Likewise, the present disclosure is not limited to various embodimentsgiven in this specification.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

As used herein, “around”, “about”, “approximately” or “substantially”shall generally refer to any approximate value of a given value orrange, in which it is varied depending on various arts in which itpertains, and the scope of which should be accorded with the broadestinterpretation understood by the person skilled in the art to which itpertains, so as to encompass all such modifications and similarstructures. In some embodiments, it shall generally mean within 20percent, preferably within 10 percent, and more preferably within 5percent of a given value or range. Numerical quantities given herein areapproximate, meaning that the term “around”, “about”, “approximately” or“substantially” can be inferred if not expressly stated, or meaningother approximate values.

Reference is now made to FIG. 1A. FIG. 1A is an equivalent circuit ofpart of an integrated circuit 100, in accordance with variousembodiments. For illustration, the integrated circuit includes logicgates 110-120. A first terminal and second terminals of the logic gate110 are coupled to signals A1-A2 respectively. A third terminal of thelogic gate 110 is coupled to a first terminal of the logic gate 120through resistors R1-R2. The resistors R1-R2 are coupled in parallel. Asecond terminal of the logic gate 120 is as an output terminal Z. Insome embodiments, the logic gate 110 is a NAND gate and the logic gate120 is an inverter. In various embodiments, the logic gate 110 isreferred as a first stage circuit, and the logic gate 120 is referred asa second stage circuit. The configurations of the integrated circuit 100are given for illustrative purposes. Various implements of theintegrated circuit 100 are within the contemplated scope of the presentdisclosure. For example, in some embodiments, the integrated circuit 100is a logic gate circuit including AND, OR, NAND, MUX, Flip-flop, Latch,BUFF or any other types of logic circuit.

In some embodiments, the resistor R1 represents a resistance contributedby part of the routing arranged to couple the first terminal of thelogic gate 110 with the logic gate 120. Similarly, the resistor R2represents a resistance contributed by another part of the routingarranged to couple the first terminal of the logic gate 110 with thelogic gate 120. The details of the configuration of the resistors R1 andR2 will be discussed in the following paragraphs.

Reference is now made to FIG. 1B. FIG. 1B is a detailed circuitcorresponding to the equivalent circuit of part of the integratedcircuit 100 in FIG. 1A, in accordance with various embodiments. Forillustration, the integrated circuit 100 includes transistors M1-M6coupled between supply voltages VDD and VSS. With respect to the logicgates 110-120 of FIG. 1A, in some embodiments, the logic gate 110includes the transistors M1-M4. The logic gate 120 includes thetransistors M5-M6.

In some embodiments, the transistors M1, M3, and M5 are P-typetransistors, and the transistors M2, M4, and M6 are N-type transistors.The configurations of the transistors M1-M6 are given for illustrativepurposes. Various implements of FIG. 1A are within the contemplatedscope of the present disclosure. For example, in some embodiments, thetransistors M1, M3, and M5 are N-type transistors, and the transistorsM2, M4, and M6 are P-type transistors.

With reference to FIG. 1B, gates of the transistors M1-M2 are coupledwith each other and are configured to be, for example, as the firstterminal of the logic gate 110 to be coupled to the signal A1. Gates ofthe transistors M3-M4 are coupled with each other and are configured tobe, for example, the second terminal of the logic gate 110 to be coupledto the signal A2. Gates of the transistors M5-M6 are coupled to eachother, drain terminals of the transistors M1 and M3, and a source/drainterminal of the transistor M2 through the resistors R1-R2. The gates ofthe transistors M5-M6 are configured to be the first terminal of thelogic gate 120. Source terminals of the transistor M1, M3, and M5 arecoupled to the supply voltage VDD. A drain/source terminal of thetransistor M2 is coupled to a drain terminal of the transistor M4.Source terminals of the transistors M4 and M6 are coupled to the supplyvoltage VSS. Drain terminals of the transistor M5 and M6 are coupled toeach other and are configured to be the second terminal of the logicgate 120.

Reference is now made to FIG. 2A. FIG. 2A is a layout diagram in a planview of part of the integrated circuit 100 corresponding to a part ofFIG. 1B, in accordance with various embodiments. For illustration, theintegrated circuit 100 includes active areas 130A-130B, conductivepatterns (metal-to-device, MD) 141-147, gates 151-157, conductivesegments (metal-zero segments, M0) 161-167, conductive line 171(metal-one segments, M1), vias VD1-VD3, VG1-VG8, VM1-VM2, and VP1-VP2.In some embodiments, the active areas 130A-130B are disposed in a firstlayer and the gates 151-157 cross the active areas 130A-130B. Theconductive patterns 141-147 are disposed in a second layer above thefirst layer. The conductive line 171 is disposed in a third layer abovethe second layer. The vias VD1-VD3, VG1-VG8, and VP1-VP2 are arrangedbetween the first layer and the second layer. The vias VM1-VM2 arearranged between the second layer and the third layer.

With reference to FIGS. 1B and 2A, the active areas 130A-130B areconfigured for the formation of the transistors M1-M6. The conductivepattern 141 corresponds to the source terminal of the transistor M1. Theconductive pattern 142 corresponds to the drain terminals of thetransistors M1 and M3. The conductive pattern 143 corresponds to thesource terminals of the transistors M3 and M5. The conductive pattern144 corresponds to the drain terminals of the transistors M5-M6. Theconductive pattern 145 corresponds to the source/drain terminal of thetransistor M2. The conductive pattern 146 corresponds to thedrain/source terminal of the transistor M2 and the drain terminal of thetransistor M4. The conductive segment 167 corresponds to the sourceterminals of the transistors M4 and M6.

The gate 152 corresponds to the gates of the transistors M1-M2. The gate153 corresponds to the gates of the transistors M3-M4. The gate 154corresponds to the gates of the transistors M5-M6. Alternatively stated,the gate 152 is shared by the transistors M1-M2. The gate 153 is sharedby the transistors M3-M4. The gate 154 is shared by the transistorsM5-M6. The gates 151, and 155-157 are referred to as dummy gates, inwhich in some embodiments, the “dummy” gate is referred to as being notelectrically connected as the gate for MOS devices, having no functionin the circuit.

As shown in FIG. 2A, for illustration, the active areas 130A-130B extendin x direction and are separate from each other in y direction differentfrom x direction. The active areas 130A-130B have widths W1 in ydirection. In some embodiments, the active area 130A includes activeregions 131-134, and the active area 130B includes active regions135-138.

In some embodiments, the active areas 130A-130B are disposed on asubstrate (not shown). The substrate includes materials including, forexample, silicon and/or is doped with phosphorus, arsenic, germanium,gallium, Indium arsenide or a combination thereof. In variousembodiments, the active area 130A is doped with p-type dopantsincluding, such as boron, indium, aluminum, gallium, or a combinationthereof, and the active area 130B is doped with n-type dopants,including, such as phosphorus, arsenic, or a combination thereof.

The configurations of the active areas 130A-130B are given forillustrative purposes. Various implements of the active areas 130A-130Bare within the contemplated scope of the present disclosure. Forexample, in some embodiments, the active areas 130A-130B include morearea regions which are separate from each other along x direction andare corresponding to terminals of the transistors M1-M6 separately.

For illustration, the conductive patterns 141-147 extend in y direction.The conductive patterns 141-143, and 145-147 are disposed on and coupledto the active regions 131-133, and 135-137 separately. The conductivepattern 144 is disposed on and coupled to the active regions 134 and138.

The gates 151-157 extend in y direction. The gates 151 and 156 areseparate from each other in y direction, and the gates 155 and 157 areseparate from each other in y direction. In some embodiments, the gatesare made separated by a cut layer (not shown). As shown in FIG. 2A, thegates 151 and 155 cross the active area 130A. The gates 156 and 157cross active area 130B. The gates 152-154 cross both the active areas130A-130B.

The conductive segments 161-167 extend in x direction and are separatefrom each other in y direction. The conductive segments 161 and 163-164overlap the active area 130A. The conductive segments 162 and 166-167overlap the active area 130B.

The configurations of the conductive segments 161-167 are given forillustrative purposes. Various implements of the conductive segments161-167 are within the contemplated scope of the present disclosure. Forexample, in some embodiments, the conductive segments 161-162 do notoverlap the active areas 130A-130B. In various embodiments, the activeareas 130A-130B have larger widths than the width W1, and accordingly,the conductive segments 164-166 fully overlap the active areas130A-130B. In various embodiments, there are more conductive segments,than those are shown in FIG. 2A, for the routing of the integratedcircuit 100.

The conductive line 171 extends in y direction and overlaps the activeareas 130A-130B, and the conductive segments 161-167. In someembodiments, the conductive line 171 is interposed between the gates153-154. The configurations of the conductive line 171 are given forillustrative purposes. Various implements of the conductive line 171 arewithin the contemplated scope of the present disclosure. For example, insome embodiments, the conductive line 171 is arranged between the gates154-155, and 157.

For illustration, the via VP1 is coupled between the conductive segment161 and the conductive patterns 141 and 143. In some embodiments, theconductive segment 161 outputs the supply voltage VDD to the conductivepatterns 141 of the transistor M1 and the conductive pattern 143 of thetransistors M3 and M5 of FIG. 1B through the via VP1. The via VP2 iscoupled between the conductive segment 162 and the conductive pattern147. In some embodiments, the conductive segment 162 receives the supplyvoltage VSS for the conductive pattern 147 of the transistors M4 and M6of FIG. 1B through the via VP2.

The via VD1 is coupled between the conductive segment 161 and theconductive pattern 142. The via VD2 is coupled between the conductivesegment 167 and the conductive pattern 145. The via VD3 is coupledbetween the conductive segment 165 and the conductive pattern 144. Insome embodiments, the conductive segment 165 outputs a signal processedby the integrated circuit 100 to the output terminal Z through the viaVD3.

The via VG1 is coupled between the conductive segment 166 and the gate152. In some embodiments, the conductive segment 166 outputs the signalA1 to the gates of the transistors M1-M2 of FIG. 1B. The via VG2 iscoupled between the conductive segment 164 and the gate 153. In someembodiments, the conductive segment 164 outputs the signal A2 to thegates of the transistors M3-M4 of FIG. 1B. The vias VG3-VG4 are disposedon and coupled to the gate 154. As shown in FIG. 2A, the via VG3 couplesthe gate 154 to the conductive pattern 142 through the conductivesegment 163 and the via VD1. The via VG4 couples the gate 154 to theconductive pattern 145 through the conductive segment 167 and the viaVD2. In addition, the vias VG5-VG8 are disposed on and coupled to thegates 151, 156, 155, and 158 separately. In some embodiments, the gatesVG5 and VG7 are coupled to the conductive segment 161, and the gates VG6and VG8 are coupled to the conductive segment 162.

The via VM1 is disposed on and coupled to the conductive segment 163,and the via VM2 is disposed on and coupled to the conductive segment167. The vias VM1-VM2 are further coupled to the conductive line 171.Accordingly, the conductive segment 163 is coupled to the conductivesegment 167 through the via VM1, the conductive line 171, and the viaVM2. The configurations of the vias VM1-VM2 are given for illustrativepurposes. Various implements of the vias VM1-VM2 are within thecontemplated scope of the present disclosure. For example, in someembodiments, the vias VM1-VM2 have tapered shapes which include a largerarea contacting the conductive line 171, compared with an areacontacting the conductive segments 163 and 167.

With reference to FIGS. 1B and 2A, as discussed above, the gate 154corresponds to the gates of the transistors M5-M6, while the conductiveline 171 is further coupled to the gate 154. In such embodiments, thegate 154, the vias VG3-VG4, the conductive segments 163 and 167, thevias VM1-VM2, and the conductive line 171 are included in the routingstructure which contributes to the resistance of the resistor R1 or R2of FIG. 1B. Accordingly, when the resistance generated by the routingstructure is reduced, the equivalent resistance of the resistor R1 or R2is reduced correspondingly.

Continuing with the aforementioned discussions, in some approaches,transistors, corresponding to the transistors M5-M6, share a gatecorresponding to the gate 154, in which the gate is not coupled to anextra metal line corresponding to, for example, the conductive line 171.In such approaches, a signal transmitted in the gate 154 experienceshigh resistance contributed by the gate 154. Compared with theapproaches, with the configurations of FIG. 2A, a signal transmitted inthe gate 154 is also transmitted through the conductive line 171.Alternatively stated, two paths coupled in parallel for transmitting thesignal are provided, and accordingly the resistance generated by therouting structure between the gates of the transistors M5-M6 of FIG. 1Bis reduced. In some embodiments, with the configurations of the FIG. 2A,the resistance is about half of that of some approaches.

In addition, in some embodiments, a ratio of a width, in x direction, ofthe conductive line 171 over a width of the gate 154 ranges from about 1to about 20. In various embodiments, a ratio of a height, in z directiondifferent from x and y directions, of the conductive line 171 over aheight of the gate 154 ranges from about 1 to about 40 times.Accordingly, in such embodiments, the conductive line 171 provides agreater cross-sectional area and a correspondingly much lowerresistance, compared with the gate 154. Hence, the resistance generatedby the routing structure between the gates of the transistors M5-M6 ofFIG. 1B is further reduced.

Furthermore, in some embodiments, the resistance generated by therouting structure between the gates of the transistors M5-M6 of FIG. 1Bis further associated with the locations of the vias VG3-VG4, relativeto the active areas 130A and 130B. For example, as the embodiments shownin FIG. 2A, the conductive segments 163 and the via VG3 align with acenter of a width of the active area 130A in y direction, and theconductive segments 167 and the via VG4 align with a center of a widthof the active area 130B in y direction. In such embodiments, forexample, the signal transmitted through the conductive segment 163 andthe via VG3 passes directly into the gate 154 and the active area 130Awithout propagating a long distance in the gate 154. Alternativelystated, the signal experiences less resistance, compared with someapproaches, in which the via, corresponding to the via VG3, is arrangedaway from the center of the active area 130A, and accordingly the signalpropagates in the gate 154 a distance before entering into the activearea. The arrangements of the conductive segment 167 and the via VG4 aresimilar to that of the conductive segments 163 and the via VG3.Therefore, the repetitious descriptions are omitted here for brevity.

With the configurations of FIG. 2A, in some embodiments, the integratedcircuit 100 obtains about 10% faster in speed compared with someapproaches. In various embodiments, as the transistors M5-M6 areimplemented multiple corresponding transistors, the integrated circuit100 obtains about 5% faster in speed compared with some approaches.

The configurations of FIG. 2A are given for illustration purposes.Various implements of FIG. 2A are within the contemplated scope of thepresent disclosure. For example, in some embodiments, widths of theconductive segments 163 and 167 are greater than that of the conductiveline 171.

Reference is now made to FIG. 2B. FIG. 2B is a cross-sectional view ofpart of the integrated circuit 100 in FIG. 2A along line AA′ in FIG. 2A,in accordance with various embodiments. For illustration, the gate 154disposes over the active areas 130A-130B, and a part of the gate 154abuts both the active areas 130A-130B. The vias VG3-VG4 align thecenters, in y direction, of the active areas 130A-130B, and are separatefrom each other in y direction.

In some embodiments, the vias VG3-VG4 have tapered shapes which includea larger area contacting the conductive segment 163 or 167, comparedwith an area contacting the gate 154. The configurations of FIG. 2B aregiven for illustration purposes. Various implements of FIG. 2B arewithin the contemplated scope of the present disclosure. For example, insome embodiments, the vias VG3-VG4 include uniform shape along zdirection. In alternative embodiments, the vias VG3-VG4 include asmaller area contacting the conductive segment 163 or 167, compared withthe area contacting the gate 154.

Reference is now made to FIG. 3 . FIG. 3 is another layout diagram inthe plan view of part of the integrated circuit 100 corresponding to apart of FIG. 1B, in accordance with various embodiments. With respect tothe embodiments of FIG. 3 , like elements in FIG. 2A are designated withthe same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 3 .

Compared with FIG. 2A, the integrated circuit 100 further includes aconductive line 172 and vias VM3-VM4. The conductive line 171 isconfigured with respect to, for example, the conductive line 171. Thevias VM3-VM4 are configured with respect to, for example, the viasVM1-VM2. The conductive line 172 is disposed between the gates 152-153and crosses the active areas 130A-130B. Specifically, the via VM3 isdisposed on and coupled to the conductive segment 163, and the via VM4is disposed on and coupled to the conductive segment 167. The viasVM3-VM4 are coupled to the conductive line 172. Alternatively stated,the gate 154 is further coupled to the conductive line 172.

With reference to FIGS. 1B, 2A, and 3 , in such embodiments of FIG. 3 ,the conductive line 172 is also included in the routing structure whichcontributes to the resistance of the resistor R1 or R2 of FIG. 1B.Because the extra path for transmitting the signal in the gate 154 isprovided by the vias VM3-VM4 and the conductive line 172, andaccordingly the resistance generated by the routing structure betweenthe gates of the transistors M5-M6 of FIG. 1B is reduced.

The configurations of FIG. 3 are given for illustration purposes.Various implements of FIG. 3 are within the contemplated scope of thepresent disclosure. For example, in some embodiments, the conductiveline 172 is disposed between the gates 151, 156, and 152. In variousembodiments, the conductive line 172 includes at least two conductivelines that one of two is disposed between the gates 151, 156, and 152,and the other is disposed between the gates 154, 155, and 157. Invarious embodiments, the gate 154 of FIG. 3 is divided into two portionsas gates 154 a-154 b later illustrated in FIG. 6A.

Reference is now made to FIG. 4A. FIG. 4A is another layout diagram inthe plan view of part of the integrated circuit 100 corresponding to apart of FIG. 1B, in accordance with various embodiments. With respect tothe embodiments of FIG. 4A, like elements in FIG. 2A are designated withthe same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 4A.

Compared with FIG. 2A, the integrated circuit 100 further includes viasVD4, VM5, and VG9, a conductive segment 168. The vias VD4, VM5, and VG9are configured with respect to the vias VD1, VM1, and VG3, separately.The conductive segment 168 is configured with respect to, for example,the conductive segment 163. For illustration, the via VD4 is disposed onand coupled to the conductive pattern 142. The via VG9 is disposed onand coupled to the gate 154. The via VM5 is disposed on and coupled tothe conductive segment 168. The conductive segment 168 is coupled to theconductive line 171 through the via VM5.

With reference to FIGS. 1B, 2A, and 4A, in such embodiments of FIG. 4A,the vias VD4, VM5, and VG9, the conductive segment 168 are also includedin the routing structure which contributes to the resistance of theresistor R1 or R2 of FIG. 1B. Because the extra path for transmittingthe signal in the gate 154 is provided by the vias VD4, VM5, and VG9,the conductive segment 168, and accordingly the resistance generated bythe routing structure between the gates of the transistors M5-M6 of FIG.1B is reduced.

In addition, as the embodiments shown in FIG. 4A, a number of the vias,configured with respect to the via VG3, is associated with the width ofthe active area 130A, and a number of the vias, configured with respectto the via VG4, is associated with the width of the active area 130B.Specifically, compared with FIG. 2A, the active area 130A has a width W2different from the width W1. In some embodiments, the width W2 isgreater than the width W1. Accordingly, in such embodiments, the numberof the vias disposed on the portion of the gate 154 crossing the activearea 130A is greater than the number of the vias disposed on the portionof the gate 154 crossing the active area 130B. Alternatively stated, thewidth of the active area 130 increases from the width W1 to the widthW2, the number of the vias disposed on the portion of the gate 154crossing the active area 130A increases correspondingly.

As discussed above, in some embodiments, a length of the gate 154 ofFIG. 4A is longer than that of the gate 154 of FIGS. 2A and 3 .Alternatively stated, the number of the vias configured with respect tothe via VG3 and the number of the vias configured with respect to thevia VG4 are also associated with the length of the gate 154.

Moreover, in some embodiments, the conductive segments 163 and 168 mergewith each other and are configured to be a conductive segment having awidth greater than the width of individual conductive segment 163 or168. In such arrangements, the resistance generated by the routingstructure between the gates of the transistors M5-M6 of FIG. 1B isfurther reduced due to greater conductive area of the conductivesegment.

The configurations of FIG. 4A are given for illustration purposes.Various implements of FIG. 4A are within the contemplated scope of thepresent disclosure. For example, in some embodiments, the conductiveline 172 in the embodiments of FIG. 3 is further included in theembodiments of FIG. 4A. The conductive line 172 is coupled with theconductive segments 163, 167, and 168 through VM3-VM4 and an extra viaconfigured with respect to the via VM3. In various embodiments, thenumber of the vias configured with respect to the vias VG3 and VG9 ismore than two. Accordingly, the number of the conductive segmentsconfigured with respect to the conductive segments 163 and 168 is morethan two. In various embodiments, the gate 154 of FIG. 4A is dividedinto two portions as gates 154 a-154 b later illustrated in FIG. 6A.

Reference is now made to FIG. 4B. FIG. 4B is a cross-sectional view ofpart of the integrated circuit 100 in FIG. 4A, in accordance withvarious embodiments. With respect to the embodiments of FIG. 4B, likeelements in FIG. 2B are designated with the same reference numbers forease of understanding. The specific operations of similar elements,which are already discussed in detail in above paragraphs, are omittedherein for the sake of brevity, unless there is a need to introduce theco-operation relationship with the elements shown in FIG. 4B.

Compared with FIG. 2B, the integrated circuit 100 further includes thevia VG9 and the conductive segment 168. The VG9 is disposed away fromthe via VG3 by a distance. The configurations of FIG. 4B are given forillustration purposes. Various implements of FIG. 4B are within thecontemplated scope of the present disclosure. For example, in someembodiments, the via VG9 aligns the centers, in y direction, of theactive area 130A having the width W2.

Reference is now made to FIG. 5A. FIG. 5A is another layout diagram inthe plan view of part of the integrated circuit 100 corresponding to apart of FIG. 1B, in accordance with various embodiments. With respect tothe embodiments of FIG. 5A, like elements in FIG. 4A are designated withthe same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 5A.

Compared with FIG. 4A, the integrated circuit 100 further includes viasVM6 and VG10, a conductive segment 169. The vias VM6 and VG10 areconfigured with respect to the vias VM2, and VG4, separately. Theconductive segment 169 is configured with respect to, for example, theconductive segment 167. For illustration, The via VG10 is disposed onand coupled to the gate 154. The via VM6 is disposed on and coupled tothe conductive segment 169. The conductive segment 169 is coupled to theconductive line 171 through the via VM6.

With reference to FIGS. 1B, 4A, and 5A, in such embodiments of FIG. 5A,the vias VM6 and VG10, the conductive segment 169 are also included inthe routing structure which contributes to the resistance of theresistor R1 or R2 of FIG. 1B. Because the extra path for transmittingthe signal in the gate 154 is provided by the vias VM6 and VG10, theconductive segment 169, and accordingly the resistance generated by therouting structure between the gates of the transistors M5-M6 of FIG. 1Bis reduced.

In addition, as the embodiments shown in FIG. 5A, the active area 130Bhas a width W3. In some embodiments, the width W3 is the same as thewidth W2. In various embodiments, the width W3 is different from thewidth W2. Accordingly, in such arrangements, the number of the viasdisposed on the portion of the gate 154 crossing the active area 130A isdifferent from the number of the vias disposed on the portion of thegate 154 crossing the active area 130B. The relationship between thevias disposed on the portion of the gate 154 crossing the active area130B and the width of the active area 130B is similar the relationshipbetween the vias disposed on the portion of the gate 154 crossing theactive area 130A and the width of the active area 130A. Therefore, therepetitious descriptions are omitted here for brevity.

Reference is now made to FIG. 5B. FIG. 5B is a cross-sectional view ofpart of the integrated circuit 100 in FIG. 5A, in accordance withvarious embodiments. With respect to the embodiments of FIG. 5B, likeelements in FIG. 4B are designated with the same reference numbers forease of understanding. The specific operations of similar elements,which are already discussed in detail in above paragraphs, are omittedherein for the sake of brevity, unless there is a need to introduce theco-operation relationship with the elements shown in FIG. 5B.

Compared with FIG. 4B, the integrated circuit 100 further includes thevia VG10 and the conductive segment 169. The VG10 is disposed away fromthe via VG4 by a distance. The configurations of FIG. 5B are given forillustration purposes. Various implements of FIG. 5B are within thecontemplated scope of the present disclosure. For example, in someembodiments, the via VG10 aligns the centers, in y direction, of theactive area 130B having the width W3.

The configurations of FIGS. 5A-5B are given for illustration purposes.Various implements of FIGS. 5A-5B are within the contemplated scope ofthe present disclosure. For example, in some embodiments, by changingthe width of the active area 130B, for example, reducing the width W3,the via VG4 does not overlap the active area 130B in the layout view. Invarious embodiments, the gate 154 of FIG. 5A is divided into twoportions as gates 154 a-154 b later illustrated in FIG. 6A.

Reference is now made to FIG. 6A. FIG. 6A is another layout diagram inthe plan view of part of the integrated circuit 100 corresponding to apart of FIG. 1B, in accordance with various embodiments. With respect tothe embodiments of FIG. 6A, like elements in FIG. 2A are designated withthe same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 6A.

Compared with FIG. 2A, as shown in FIG. 6A, instead of having the singlegate 154, the integrated circuit 100 includes gates 154 a-154 b. Thegates 154 a-154 b are configured with respect to the gate 154 of FIG.2A. For illustration, the gates 154 a-154 b align with each other in a ydirection, and are separate from each other in y direction. The via VG3is disposed on the gate 154 a, and the via VG4 is disposed on the gate154 b.

In some embodiments, the gates 154 a-154 b are formed by implementing acut layer (not shown) at the middle of the gate 154. In someembodiments, the cut layer has a width, in y direction, which is thesame as the width of the conductive segment 165.

Reference is now made to FIG. 6B. FIG. 6B is a cross-sectional view ofpart of the integrated circuit 100 in FIG. 6A, in accordance withvarious embodiments. With respect to the embodiments of FIG. 6B, likeelements in FIG. 2B are designated with the same reference numbers forease of understanding. The specific operations of similar elements,which are already discussed in detail in above paragraphs, are omittedherein for the sake of brevity, unless there is a need to introduce theco-operation relationship with the elements shown in FIG. 6B.

Compared with FIG. 2B, instead of the gate 154 being a single gatestructure, the two separate gates 154 a-154 b are separate from eachother in y direction.

The configurations of FIGS. 6A-6B are given for illustration purposes.Various implements of FIGS. 6A-6B are within the contemplated scope ofthe present disclosure. For example, in some embodiments, the viasVG3-VG4 do not align the centers of the active areas 130A-130B.

Based on the above discussions of FIGS. 1A-6B, in some embodiments, asthe logic gate 120 includes the transistors M5-M6, a threshold voltageof the logic gate 120 having the separated gates 154 a-154 b is lowerthan that of the logic gate 120 having the single gate 154.

Furthermore, in various embodiments, since the conductive path throughgate structure in FIG. 6A is cut (i.e., the gates 154 a-154 bcorresponding to the gate 154 are separate from each other), instead ofhaving two conductive paths as illustrated in FIG. 2A, there is oneconductive path provided by the conductive line 171. Accordingly, theresistance generated by the routing structure of FIG. 6A is, forexample, about 2% higher than that of FIG. 2A, in some embodiments.

Reference is now made to FIG. 7A. FIG. 7A is an equivalent circuit ofpart of an integrated circuit 700, in accordance with variousembodiments. For illustration, the integrated circuit includes logicgates 710-720. A first terminal of the logic gate 710 is coupled to asignal B1. A second terminal of the logic gate 710 is coupled to a firstterminal of the logic gate 720 through resistors R3-R4. The resistorsR3-R4 are coupled in parallel. A second terminal of the logic gate 720is coupled to a signal B2. A third terminal of the logic gate 720 is asan output terminal ZN. In some embodiments, the logic gate 710 is aninverter and the logic gate 720 is a NAND gate. In various embodiments,the logic gate 710 is referred as a first stage circuit, and the logicgate 720 is referred as a second stage circuit. The configurations ofthe integrated circuit 700 are given for illustrative purposes. Variousimplements of the integrated circuit 700 are within the contemplatedscope of the present disclosure. For example, in some embodiments, theintegrated circuit 700 is a logic gate circuit including AND, OR, NAND,MUX, Flip-flop, Latch, BUFF or any other types of logic circuit.

In some embodiments, the resistor R3 represents a resistance contributedby part of the routing arranged to couple the first terminal of thelogic gate 710 with the logic gate 720. Similarly, the resistor R4represents a resistance contributed by another part of the routingarranged to couple the first terminal of the logic gate 710 with thelogic gate 720. The details of the configuration of the resistors R3 andR4 will be discussed in the following paragraphs.

Reference is now made to FIG. 7B. FIG. 7B is a detailed circuitcorresponding to the equivalent circuit of part of the integratedcircuit 700 in FIG. 7A, in accordance with various embodiments. Forillustration, the integrated circuit 700 includes transistors T1-T6coupled between the supply voltages VDD and VSS. With respect to thelogic gates 710-720 of FIG. 7A, in some embodiments, the logic gate 710includes the transistors T1-T2. The logic gate 720 includes thetransistors T3-T6.

In some embodiments, the transistors T1, T3, and T5 are P-typetransistors, and the transistors T2, T4, and T6 are N-type transistors.The configurations of the transistors T1-T6 are given for illustrativepurposes. Various implements of FIG. 1A are within the contemplatedscope of the present disclosure. For example, in some embodiments, thetransistors T1, T3, and T5 are N-type transistors, and the transistorsT2, T4, and T6 are P-type transistors.

With reference to FIG. 7B, gates of the transistors T1-T2 are coupledwith each other and are configured to be, for example, as the firstterminal of the logic gate 710 to be coupled to the signal B1. Gates ofthe transistors T3-T4 are coupled to each other, and drain terminals ofthe transistors T1 and T2 through the resistors R3-R4, and the gates ofthe transistors T3-T4 are configured to be, for example, the firstterminal of the logic gate 720. Gates of the transistors T5-T6 arecoupled with each other and are configured to be, for example, thesecond terminal of the logic gate 720 to be coupled to the signal B2.Source terminals of the transistor T1, T3, and T5 are coupled to thesupply voltage VDD. A drain terminal of the transistor T2 is coupled toa drain terminal of the transistor T1. Source terminals of thetransistors T2 and T4 are coupled to the supply voltage VSS. A drainterminal of the transistor T4 is coupled to a drain/source terminal ofthe transistor T6. A source/drain terminal of the transistor T6 and adrain terminal of the transistor T5 are coupled to each other and areconfigured to be the third terminal of the logic gate 720.

Reference is now made to FIG. 8A. FIG. 8A is a layout diagram in a planview of part of the integrated circuit 700 corresponding to a part ofFIG. 7B, in accordance with various embodiments. For illustration, theintegrated circuit 700 includes active areas 730A-730B, conductivepatterns (metal-to-device, MD) 741-747, gates 751-755, conductivesegments (metal-zero segments, M0) 761-762, 763 a-763 b, 764-766, and767 a-767 b, conductive lines 771 -772 (metal-one segments, M1), viasVD71-VD74, VG71-VG78, VM1-VM4, and VP71-VP72. In some embodiments, theactive areas 730A-730B are disposed in a first layer and the gates751-755 cross the active areas 730A-730B. The conductive patterns741-747 are disposed in a second layer above the first layer. Theconductive lines 771-772 are disposed in a third layer above the secondlayer. The vias VD71-VD34, VG71-VG78, and VP71-VP72 are arranged betweenthe first layer and the second layer. The vias VM1-VM4 are arrangedbetween the second layer and the third layer.

With reference to FIGS. 7B and 8A, the active areas 730A-730B areconfigured for the formation of the transistors T1-T6. The conductivepattern 741 corresponds to the drain terminals of the transistors T1-T2.The conductive pattern 742 corresponds to the source terminals of thetransistors T1 and T3. The conductive pattern 743 corresponds to thedrain terminals of the transistors T3 and T5. The conductive pattern 744corresponds to the source terminal of the transistor T5. The conductivepattern 745 corresponds to the source terminals of the transistors T2and T4. The conductive pattern 746 corresponds to the drain/sourceterminal of the transistor T6 and the drain terminal of the transistorT4. The conductive pattern 767 corresponds to the source/drain terminalof the transistor T6.

The gate 752 corresponds to the gates of the transistors T1-T2. The gate753 corresponds to the gates of the transistors T3-T4. The gate 754corresponds to the gates of the transistors T5-T6. Alternatively stated,the gate 752 is shared by the transistors T1-T2. The gate 753 is sharedby the transistors T3-T4. The gate 754 is shared by the transistorsT5-T6. The gates 751 and 755 are referred to as the dummy gates.

As shown in FIG. 8A, for illustration, the active areas 730A-730B extendin x direction and are separate from each other in y direction differentfrom x direction. The active areas 730A-730B have the widths W1 in ydirection. In some embodiments, the active area 130A includes activeregions 731-734, and the active area 130B includes active regions735-738. The arrangements of the active areas 730A-730B are similar tothat of the active areas 130A-130B of FIG. 2A. Therefore, therepetitious descriptions are omitted here for brevity.

For illustration, the conductive patterns 741-747 extend in y direction.The conductive pattern 741 is disposed on and coupled to the activeregions 731 and 735. The conductive patterns 742-747 are disposed on andcoupled to the active regions 732-734, and 736-738 separately.

The gates 751-755 extend in y direction and are separate from each otherin x direction. As shown in FIG. 8A, the gates 751-755 cross both theactive areas 730A-730B.

The conductive segments 761-762, 763 a-763 b, 764-766, and 767 a-767 bextend in x direction and are separate from each other in y direction.The conductive segments 761, 763 a-763 b, 764 overlap the active area730A. The conductive segments 762, 766, and 767 a-767 b overlap theactive area 730B.

The configurations of the conductive segments 761-762, 763 a-763 b,764-766, and 767 a-767 b are given for illustrative purposes. Variousimplements of the conductive segments 761-762, 763 a-763 b, 764-766, and767 a-767 b are within the contemplated scope of the present disclosure.For example, in some embodiments, the conductive segments 761-762 do notoverlap the active areas 730A-730B.

The conductive lines 771-772 extend in y direction and overlap theactive areas 730A-730B, and the conductive segments 761-762, 763 b,764-766, and 767 b. In some embodiments, the conductive line 771 isinterposed between the gates 754-755. The conductive line 772 isinterposed between the gates 753-754.

For illustration, the via VP71 is coupled between the conductive segment761 and the conductive patterns 742 and 744. In some embodiments, theconductive segment 761 outputs the supply voltage VDD to the conductivepatterns 742 of the transistors T1 and T3 and the conductive pattern 744of the transistors T3 and T5 of FIG. 7B through the via VP71. The viaVP72 is coupled between the conductive segment 762 and the conductivepattern 745. In some embodiments, the conductive segment 762 receivesthe supply voltage VSS for the conductive pattern 745 of the transistorsT2 and T4 of FIG. 7B through the via VP72.

The via VD71 is coupled between the conductive segment 764 and theconductive pattern 741. The via VD72 is coupled between the conductivesegment 766 and the conductive pattern 141. The via VD73 is coupledbetween the conductive segment 767 b and the conductive pattern 747. Thevia VD74 is coupled between the conductive segment 763 b and theconductive pattern 743.

The via VG71 is coupled between the conductive segment 767 a and thegate 752. In some embodiments, the conductive segment 767 a outputs thesignal B1 to the gates of the transistors T1-T2 of FIG. 7B. The via VG72is coupled between the conductive segment 765 and the gate 754. In someembodiments, the conductive segment 765 outputs the signal B2 to thegates of the transistors T5-T6 of FIG. 7B. The vias VG73-VG74 aredisposed on and coupled to the gate 753. As shown in FIG. 8A, the viaVG73 couples the gate 753 to the conductive pattern 741 through theconductive segment 764 and the via VD71. The via VG4 couples the gate753 to the conductive pattern 741 through the conductive segment 766 andthe via VD72. In addition, the vias VG75-VG76 are disposed on andcoupled to the gate 751, and the vias VG77-78 are disposed on andcoupled to the gate 755. In some embodiments, the gates VG75 and VG77are coupled to the conductive segment 761, and the gates VG76 and VG78are coupled to the conductive segment 762.

The via VM71 is disposed on and coupled to the conductive segment 764,and the via VM72 is disposed on and coupled to the conductive segment766. The vias VM71-VM72 are further coupled to the conductive line 771.Accordingly, the conductive segment 764 is coupled to the conductivesegment 766 through the via VM71, the conductive line 771, and the viaVM72. Furthermore, the via VM73 is disposed on and coupled to theconductive segment 763 b, and the via VM74 is disposed on and coupled tothe conductive segment 767 b. The vias VM3-VM4 are further coupled tothe conductive line 772. Accordingly, the conductive pattern 743 iscoupled to the conductive pattern 746 through the via VD74, theconductive segment 763 b, the via VM73, the conductive line 772, the viaVM74, the conductive segment 767 b, and the via VD73.

The configurations of the vias VM71-VM74 are given for illustrativepurposes. Various implements of the vias VM71-VM74 are within thecontemplated scope of the present disclosure. For example, in someembodiments, the vias VM71-VM72 have tapered shapes which include alarger area contacting the conductive line 771, compared with an areacontacting the conductive segments 764 and 766.

With reference to FIGS. 7B and 8A, as discussed above, the gate 753corresponds to the gates of the transistors T3-T4, while the conductiveline 771 is further coupled to the gate 753. In such embodiments, thegate 753, the vias VG73-VG74, the conductive segments 764 and 766, thevias VM71-VM72, and the conductive line 771 are included in the routingstructure which contributes to the resistance of the resistor R3 or R4of FIG. 7B. Accordingly, when the resistance generated by the routingstructure is reduced, the equivalent resistance of the resistor R3 or R4is reduced correspondingly.

Continuing with the aforementioned discussions, in some approaches,transistors, corresponding to the transistors T3-T4, share a gatecorresponding to the gate 753, in which the gate is not coupled to anextra metal line corresponding to, for example, the conductive line 771.In such approaches, a signal transmitted in the gate 753 experienceshigh resistance contributed by the gate 753. Compared with theapproaches, with the configurations of FIG. 8A, a signal transmitted inthe gate 753 is also transmitted through the conductive line 771.Alternatively stated, two paths coupled in parallel for transmitting thesignal are provided, and accordingly the resistance generated by therouting structure between the gates of the transistors T3-T4 of FIG. 7Bis reduced. In some embodiments, with the configurations of the FIG. 8A,the resistance is about ¾ of that of some approaches.

In addition, in some embodiments, the arrangements the conductive line771 is similar to that of the conductive line 171 of FIG. 2A.Accordingly, in such embodiments, the conductive line 771 provides agreater cross-sectional area and a correspondingly much lowerresistance, compared with the gate 753. Hence, the resistance generatedby the routing structure between the gates of the transistors T3-T4 ofFIG. 7B is further reduced.

Moreover, as discussed above respect to the resistance generated by therouting structure between the gates of the transistors M5-M6 of FIG. 1B,the resistance generated by the routing structure between the gates ofthe transistors T3-T4 of FIG. 7B is further associated with thelocations of the vias VG73-VG74 relative to the active areas 730A and730B. For example, as the embodiments shown in FIG. 8A, the via VG73 islocated a distance away from a center, in y direction, of the activearea 730A, and the via VG74 is located a distance away from a center, iny direction, of the active area 730B. In such embodiments, for example,the signal from/to the conductive segment 764 transmits through the viaVG73 and propagates the distance in the gate 753. Alternatively stated,the signal experiences relative greater resistance, compared with theembodiments of FIG. 2A in which the corresponding via VG3 aligns thecenter of the active area 130A. The arrangements of the conductivesegment 766 and the via VG74 are similar to that of the conductivesegments 764 and the via VG73. Therefore, the repetitious descriptionsare omitted here for brevity.

The configurations of FIG. 8A are given for illustration purposes.Various implements of FIG. 8A are within the contemplated scope of thepresent disclosure. For example, in some embodiments, the active areas730A-730B have larger widths than the width W1, and accordingly, theconductive segments 764-766 fully overlap the active areas 730A-730B. Invarious embodiments, there are more conductive segments corresponding tothe conductive segments 764 or 766 and more vias corresponding to thevias VG73 or VG74, than those are shown in FIG. 8A, for the routingbetween the transistors T3-T4 of the integrated circuit 700.

Reference is now made to FIG. 8B. FIG. 8B is a cross-sectional view ofpart of the integrated circuit 700 in FIG. 8A along line AA′ in FIG. 8A,in accordance with various embodiments. For illustration, the gate 753disposes over the active areas 730A-730B, and a part of the gate 753abuts both the active areas 730A-730B. The vias VG3-VG4 locate away thecenters, in y direction, of the active areas 730A-730B, and are separatefrom each other in y direction.

The arrangements of shapes of the vias VG73-VG74 are similar to that ofthe vias VG3-VG4 of FIG. 2B. Therefore, the repetitious descriptions areomitted here for brevity.

Reference is now made to FIG. 9A. FIG. 9A is another layout diagram inthe plan view of part of the integrated circuit 700 corresponding to apart of FIG. 7B, in accordance with various embodiments. With respect tothe embodiments of FIG. 9A, like elements in FIG. 8A are designated withthe same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 9A.

Compared with FIG. 8A, the integrated circuit 700 further includes viasVD75, VM75, and VG79, a conductive segment 768. The vias VD75, VM75, andVG79 are configured with respect to the vias VD71, VM71, and VG73,separately. The conductive segment 768 is configured with respect to,for example, the conductive segment 764. For illustration, the via VD75is disposed on and coupled to the conductive pattern 741. The via VG79is disposed on and coupled to the gate 753. The via VM75 is disposed onand coupled to the conductive segment 768. The conductive segment 768 iscoupled to the conductive line 771 through the via VM75.

With reference to FIGS. 7B, 8A, and 9A, in such embodiments of FIG. 9A,the vias VD75, VM75, and VG79, the conductive segment 768 are alsoincluded in the routing structure which contributes to the resistance ofthe resistor R3 or R4 of FIG. 7B. Because the extra path fortransmitting the signal in the gate 753 is provided by the vias VD75,VM75, and VG79, the conductive segment 768, and accordingly theresistance generated by the routing structure between the gates of thetransistors T3-T4 of FIG. 7B is reduced.

In addition, as the embodiments shown in FIG. 9A, the active area 730Ahas a width W4. In some embodiments, the width W4 is greater than thewidth W1 of the active area 730B. Accordingly, in such embodiments, anumber of the vias disposed on the portion of the gate 753 crossing theactive area 730A is greater than a number of the vias disposed on theportion of the gate 753 crossing the active area 730B. The relationshipbetween the number of vias, configured with respect to the vias VG73 orVG74, and widths of the active areas 730A-730B is similar to that isdiscussed with respect to the vias VG3-VG4 and the active areas130A-130B. Therefore, the repetitious descriptions are omitted here forbrevity.

The configurations of FIG. 9A are given for illustration purposes.Various implements of FIG. 9A are within the contemplated scope of thepresent disclosure. For example, in some embodiments, the number of thevias configured with respect to the vias VG73 and VG79 is more than two.Accordingly, the number of the conductive segments configured withrespect to the conductive segments 764 and 768 is more than two. Invarious embodiments, the gate 753 of FIG. 9A is divided into twoportions as gates 753 a-753 b later illustrated in FIG. 10A.

Moreover, in various embodiments, the width of the active area 730B isgreater than the width W1. A number of the vias configured with respectto the via VG74 is more than one. The number of the conductive segmentsconfigured with respect to the conductive segment 766 is correspondinglymore than one. Alternatively stated, the integrated circuit 700 furtherincludes extra paths provided by structures mentioned above fortransmitting the signal in the gate 753. Accordingly the resistancegenerated by the routing structure between the gates of the transistorsT3-T4 of FIG. 7B is reduced.

Reference is now made to FIG. 9B. FIG. 9B is a cross-sectional view ofpart of the integrated circuit 700 in FIG. 9A, in accordance withvarious embodiments. With respect to the embodiments of FIG. 9B, likeelements in FIG. 8B are designated with the same reference numbers forease of understanding. The specific operations of similar elements,which are already discussed in detail in above paragraphs, are omittedherein for the sake of brevity, unless there is a need to introduce theco-operation relationship with the elements shown in FIG. 9B.

Compared with FIG. 8B, the integrated circuit 700 further includes thevia VG79 and the conductive segment 768. The VG79 is disposed away fromthe via VG73 by a distance. The configurations of FIG. 9B are given forillustration purposes. Various implements of FIG. 9B are within thecontemplated scope of the present disclosure. For example, in someembodiments, the via VG79 aligns the centers, in y direction, of theactive area 730A having the width W4.

Reference is now made to FIG. 10A. FIG. 10A is another layout diagram inthe plan view of part of the integrated circuit 700 corresponding to apart of FIG. 7B, in accordance with various embodiments. With respect tothe embodiments of FIG. 10A, like elements in FIG. 8A are designatedwith the same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 10A.

Compared with FIG. 8A, as shown in FIG. 10A, instead of having thesingle gate 753, the integrated circuit 700 includes gates 753 a-753 b.The gates 753 a-753 b are configured with respect to the gate 753 ofFIG. 8A. For illustration, the gates 753 a-753 b align with each otherin a y direction, and are separate from each other in y direction. Thevia VG73 is disposed on the gate 753 a, and the via VG74 is disposed onthe gate 753 b.

In some embodiments, the gates 753 a-753 b are formed by implementing acut layer (not shown) at the middle of the gate 753. In someembodiments, the cut layer has a width, in y direction, which is thesame as the width of the conductive segment 765.

Furthermore, in various embodiments, since the conductive path throughgate structure in FIG. 10A is cut (i.e., the gates 753 a-753 bcorresponding to the gate 753 is separate from each other), instead ofhaving two paths as illustrated in FIG. 9A, there is only one conductivepath provided by the conductive line 771. Accordingly, the resistancegenerated by the routing structure of FIG. 10A can be, for example,about 4% higher than that of FIG. 9A.

Reference is now made to FIG. 10B. FIG. 10B is a cross-sectional view ofpart of the integrated circuit 700 in FIG. 10A, in accordance withvarious embodiments. With respect to the embodiments of FIG. 10B, likeelements in FIG. 8B are designated with the same reference numbers forease of understanding. The specific operations of similar elements,which are already discussed in detail in above paragraphs, are omittedherein for the sake of brevity, unless there is a need to introduce theco-operation relationship with the elements shown in FIG. 10B.

Compared with FIG. 8B, instead of the gate 753 being a single gatestructure, the two separate gates 753 a-753 b are separate from eachother in y direction.

The configurations of FIGS. 10A-10B are given for illustration purposes.Various implements of FIGS. 10A-10B are within the contemplated scope ofthe present disclosure. For example, in some embodiments, the widths ofthe active areas 730A-730B are wider than the width W1, and accordinglythe integrated circuit 700 includes more vias corresponding to the viasVG73 or VG74.

Reference is now made to FIG. 11 . FIG. 11 is another layout diagram inthe plan view of part of the integrated circuit 700 corresponding to apart of FIG. 7B, in accordance with various embodiments. With respect tothe embodiments of FIG. 11 , like elements in FIG. 8A are designatedwith the same reference numbers for ease of understanding. The specificoperations of similar elements, which are already discussed in detail inabove paragraphs, are omitted herein for the sake of brevity, unlessthere is a need to introduce the co-operation relationship with theelements shown in FIG. 11 .

Compared with FIG. 8A, as shown in FIG. 11 , the integrated circuit 700further includes vias VM76-VM77, and VG710-VG711, a conductive line 773.The vias VM76 and VM77 are configured with respect to the vias VM71 andVM72, respectively. The vias VG710 and VG711 are configured with respectto the vias VG73 and VG74, respectively. The conductive line 773 isconfigured with respect to, for example, the conductive line 771. Forillustration, the via VM76 is disposed on and coupled to the conductivesegment 763 a. The via VM77 is disposed on and coupled to the conductivesegment 767 b. The vias VM76-VM77 are further coupled to the conductiveline 773. The vias VG710-VG711 are disposed on and coupled to the gate752. Accordingly, in such arrangements, the gate 752 is coupled with theconductive line 773 through the vias VG710-711, the conductive segments763 a and 767 a, and the conductive line 773.

With reference to FIGS. 7B, 8A and 11 , in such embodiments of FIG. 11 ,the vias VM76-VM77, and VG710-VG711, the conductive line 773 are alsoincluded in a routing structure, between the gates of the transistorsT1-T2 of FIG. 7B, which contributes a resistance. Because an extra pathfor transmitting a signal in the gate 752 is provided by the viasVM76-VM77, and VG710-VG711, the conductive line 773, and accordingly theresistance generated by the routing structure between the gates of thetransistors T1-T2 of FIG. 7B is reduced.

The features of the relationship between the vias VM76-VM77,VG710-VG711, the conductive line 773 and the resistance generated by therouting structure thereof are similar to that of the vias VM71-VM72,VG73-VG74, and the conductive line 771. Therefore, the repetitiousdescriptions are omitted here for brevity.

The configurations of FIG. 11 are given for illustration purposes.Various implements of FIG. 11 are within the contemplated scope of thepresent disclosure. For example, in some embodiments, as the widths ofthe active areas 730A and/or 730B increase, the vias VM71-VM76,VG73-VG74, VG710-VG711, the conductive segments 763 a, 767 a, 764, 766,or the combinations thereof are implements with multiple correspondingstructures for further reducing the resistance generated by the routingstructures.

Reference is now made to FIG. 12 . FIG. 12 is a flow chart of a method1200 for manufacturing the integrated circuits 100 or 700, in accordancewith some embodiments of the present disclosure. It is understood thatadditional operations can be provided before, during, and after theprocesses shown by FIG. 12 , and some of the operations described belowcan be replaced or eliminated, for additional embodiments of the method1200. The method 1200 includes operations 1210-1230 that are describedbelow with reference to the integrated circuit 100 of FIG. 2A.

In operation 1210, a gate structure shared by a first transistor and asecond transistor is formed. The first transistor can be a first typeand the second transistor can be a second type, in which the second typeis different from the first type. Referring to FIGS. 1B and 1C, the gate154 is formed and shared by the transistor M5 of P type and thetransistor M6 of N type.

In operation 1220, at least one first gate via and at least one secondgate via are formed on the gate structure. Referring to FIG. 1C, thevias VG3 and VG4 are formed on the gate 154. In some embodiments, thevias VG3 and VG4 are electrically coupled to the gate 154.

In operation 1230, a conductive line coupled to the gatestructure—through a plurality of conductive vias, a plurality ofconductive segments, the at least one first gate via, and the at leastone second gate via—is formed. In some embodiments, the gate structureand the conductive line extend in a first direction (e.g., ay-direction). Referring to FIG. 1C, the conductive line 171 is formedand coupled to the gate 154 through the vias VM1-VM2, VG3-VG4, and theconductive segments 163 and 167. As shown in FIG. 2A, in someembodiments, the gate 154 and the conductive line 171 extend in they-direction.

In some embodiments, the ratio of the width of the conductive line 171over a width of the gate 154 ranges from about 1 to about 20, and theratio of the height of the conductive line 171 over the height of thegate 154 ranges from about 1 to about 40.

In some embodiments, the method 1200 further includes operation offorming the active area 130A of the transistor M5 and the active area130B of the transistor M6. The active areas 130A-130B are separated fromeach other in the y-direction and extend in the x-direction. In someembodiments, the via VG3 aligns with a center of the active area 130A inthe y-direction, as shown in FIG. 2A.

In some embodiments, the method 1200 further includes operation ofseparating, in y direction, a first segment of the gate 154 from asecond segment of the gate 154. The first segment is, for example, thegate 154 a of FIG. 6A, and the second segment is, for example, the gate154 b of FIG. 6A.

In some embodiments, as discussed above, a resistance of a conductivepath with the separated segments, for example, the gates 154 a-154 b ofthe gate 154 is greater than that when the first segment and secondsegment of the gate 154 are merged.

FIG. 13 illustrates a comparison table of gate resistance, in accordancewith some embodiments of the present disclosure. As discussed above, thegate resistance (including the metal routing coupled to the gatestructure) varies in response to different layouts. In some embodiments,case A corresponds to some approaches that provide a continuous gatestructure and a via disposed thereon, without other segments configuredwith respect to conductive line 171 or 771 of the present disclosure.Case B corresponds to the embodiments of FIG. 8A. Case C corresponds tothe embodiments of FIG. 10A. Case D corresponds to the embodiments ofFIG. 2A. Case E corresponds to the embodiments of FIG. 6A.

As shown in FIG. 13 , comparing case B with case A having the gateresistance being referred as 1×, the gate resistance of case B is0.75×and smaller than that of case A, due to having more than one viasVG73-VG74 and additional conductive line 771 as shown in FIG. 8A.Alternatively stated, case B provides more conductive paths than case A.

Comparing case C with case B, the gate structure is cut in case C. Lessconductive path is included in case C, and accordingly, the gateresistance of case C is 0.79×and greater than that of case B.

Comparing case D with case B, vias in case D are located in centers ofactive areas. As discussed above, in some embodiments, signaltransmitted through conductive segments (MO layer in FIG. 13 ) and thevias passes directly into the gate and the active areas withoutpropagating a long distance in the gate. Accordingly, the gateresistance of case D is 0.52×and smaller than that of case B.

Comparing case E with case D, the gate structure is cut in case E. Lessconductive path is included in case E, and accordingly, the gateresistance of case E is 0.54×and greater than that of case D.

In addition, even the gate resistance of case C is greater than that ofcase B, effect of parasitic capacitance of metal routing in case C issmaller than that of case B due to separated gate, in some embodiments.The comparison of effect of parasitic capacitance between cases D and Eare similar to cases B and C. Thus, the repetitious descriptions areomitted here.

The configurations of FIG. 13 are given for illustrative purposes.Various implements are within the contemplated scope of the presentdisclosure. For example, in some embodiments, the gate resistancereduces when more vias are coupled to the gate as shown in theembodiments of FIG. 5A.

Reference is now made to FIG. 14 . FIG. 14 is a block diagram of anelectronic design automation (EDA) system 1400 for designing theintegrated circuit layout design, in accordance with some embodiments ofthe present disclosure. EDA system 1400 is configured to implement oneor more operations of the method 1200 disclosed in FIG. 12 , and furtherexplained in conjunction with FIGS. 1A-11 . In some embodiments, EDAsystem 1400 includes an APR system.

In some embodiments, EDA system 1400 is a general purpose computingdevice including a hardware processor 1402 and a non-transitory,computer-readable storage medium 1404. Storage medium 1404, amongstother things, is encoded with, i.e., stores, computer program code(instructions) 1406, i.e., a set of executable instructions. Executionof instructions 1406 by hardware processor 1402 represents (at least inpart) an EDA tool which implements a portion or all of, e.g., the method1200.

The processor 1402 is electrically coupled to computer-readable storagemedium 1404 via a bus 1408. The processor 1402 is also electricallycoupled to an I/O interface 1410 and a fabrication tool 1416 by bus1408. A network interface 1412 is also electrically connected toprocessor 1402 via bus 1408. Network interface 1412 is connected to anetwork 1414, so that processor 1402 and computer-readable storagemedium 1404 are capable of connecting to external elements via network1414. The processor 1402 is configured to execute computer program code1406 encoded in computer-readable storage medium 1404 in order to causeEDA system 1400 to be usable for performing a portion or all of thenoted processes and/or methods. In one or more embodiments, processor1402 is a central processing unit (CPU), a multi-processor, adistributed processing system, an application specific integratedcircuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 1404 is anelectronic, magnetic, optical, electromagnetic, infrared, and/or asemiconductor system (or apparatus or device). For example,computer-readable storage medium 1404 includes a semiconductor orsolid-state memory, a magnetic tape, a removable computer diskette, arandom access memory (RAM), a read-only memory (ROM), a rigid magneticdisk, and/or an optical disk. In one or more embodiments using opticaldisks, computer-readable storage medium 1404 includes a compactdisk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W),and/or a digital video disc (DVD).

In one or more embodiments, storage medium 1404 stores computer programcode 1406 configured to cause EDA system 1400 (where such executionrepresents (at least in part) the EDA tool) to be usable for performinga portion or all of the noted processes and/or methods. In one or moreembodiments, storage medium 1404 also stores information whichfacilitates performing a portion or all of the noted processes and/ormethods. In one or more embodiments, storage medium 1404 stores IClayout diagram 1420 of standard cells including such standard cells asdisclosed herein, for example, a cell including in the integratedcircuits 100 and/or 700 discussed above with respect to FIGS. 1A-11 .

EDA system 1400 includes I/O interface 1410. I/O interface 1410 iscoupled to external circuitry. In one or more embodiments, I/O interface1410 includes a keyboard, keypad, mouse, trackball, trackpad,touchscreen, and/or cursor direction keys for communicating informationand commands to processor 1402.

EDA system 1400 also includes network interface 1412 coupled toprocessor 1402. Network interface 1412 allows EDA system 1400 tocommunicate with network 1414, to which one or more other computersystems are connected. Network interface 1412 includes wireless networkinterfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wirednetwork interfaces such as ETHERNET, USB, or IEEE-1464. In one or moreembodiments, a portion or all of noted processes and/or methods areimplemented in two or more systems 1400.

EDA system 1400 also includes the fabrication tool 1416 coupled toprocessor 1402. The fabrication tool 1416 is configured to fabricateintegrated circuits, e.g., the integrated circuit 100 and/or 700illustrated in FIGS. 1A-11 , according to the design files processed bythe processor 1402.

EDA system 1400 is configured to receive information through I/Ointerface 1410. The information received through I/O interface 1410includes one or more of instructions, data, design rules, libraries ofstandard cells, and/or other parameters for processing by processor1402. The information is transferred to processor 1402 via bus 1408. EDAsystem 1400 is configured to receive information related to a UI throughI/O interface 1410. The information is stored in computer- readablemedium 1404 as design specification 1422.

In some embodiments, a portion or all of the noted processes and/ormethods are implemented as a standalone software application forexecution by a processor. In some embodiments, a portion or all of thenoted processes and/or methods are implemented as a software applicationthat is a part of an additional software application. In someembodiments, a portion or all of the noted processes and/or methods areimplemented as a plug-in to a software application. In some embodiments,at least one of the noted processes and/or methods are implemented as asoftware application that is a portion of an EDA tool. In someembodiments, a portion or all of the noted processes and/or methods areimplemented as a software application that is used by EDA system 1400.In some embodiments, a layout diagram which includes standard cells isgenerated using a suitable layout generating tool.

In some embodiments, the processes are realized as functions of aprogram stored in a non-transitory computer readable recording medium.Examples of a non-transitory computer readable recording medium include,but are not limited to, external/removable and/or internal/built-instorage or memory unit, for example, one or more of an optical disk,such as a DVD, a magnetic disk, such as a hard disk, a semiconductormemory, such as a ROM, a RAM, a memory card, and the like.

FIG. 15 is a block diagram of IC manufacturing system 1500, and an ICmanufacturing flow associated therewith, in accordance with someembodiments. In some embodiments, based on a layout diagram, at leastone of (A) one or more semiconductor masks or (B) at least one componentin a layer of a semiconductor integrated circuit is fabricated using ICmanufacturing system 1500.

In FIG. 15 , IC manufacturing system 1500 includes entities, such as adesign house 1520, a mask house 1530, and an IC manufacturer/fabricator(“fab”) 1550, that interact with one another in the design, development,and manufacturing cycles and/or services related to manufacturing an ICdevice 1560. The entities in IC manufacturing system 1500 are connectedby a communications network. In some embodiments, the communicationsnetwork is a single network. In some embodiments, the communicationsnetwork is a variety of different networks, such as an intranet and theInternet. The communications network includes wired and/or wirelesscommunication channels. Each entity interacts with one or more of theother entities and provides services to and/or receives services fromone or more of the other entities. In some embodiments, two or more ofdesign house 1520, mask house 1530, and IC fab 1550 is owned by a singleentity. In some embodiments, two or more of design house 1520, maskhouse 1530, and IC fab 1550 coexist in a common facility and use commonresources.

Design house (or design team) 1520 generates an IC design layout diagram1522. IC design layout diagram 1522 includes various geometricalpatterns, for example, an IC layout design depicted in FIGS. 2A, 3, 4A,5A, 6A, 8A, 9A, 10A, and/or 11, designed for an IC device 1560, forexample, integrated circuits 100 and 700 discussed above with respect toFIGS. 2A, 3, 4A, 5A, 6A, 8A, 9A, 10A, and/or 11. The geometricalpatterns correspond to patterns of metal, oxide, or semiconductor layersthat make up the various components of IC device 1560 to be fabricated.The various layers combine to form various IC features. For example, aportion of IC design layout diagram 1522 includes various IC features,such as an active region, gate electrode, source and drain, conductivesegments or vias of an interlayer interconnection, to be formed in asemiconductor substrate (such as a silicon wafer) and various materiallayers disposed on the semiconductor substrate. Design house 1520implements a proper design procedure to form IC design layout diagram1522. The design procedure includes one or more of logic design,physical design or place and route. IC design layout diagram 1522 ispresented in one or more data files having information of thegeometrical patterns. For example, IC design layout diagram 1522 can beexpressed in a GDSII file format or DFII file format.

Mask house 1530 includes data preparation 1532 and mask fabrication1544. Mask house 1530 uses IC design layout diagram 1522 to manufactureone or more masks 1545 to be used for fabricating the various layers ofIC device 1560 according to IC design layout diagram 1522. Mask house1530 performs mask data preparation 1532, where IC design layout diagram1522 is translated into a representative data file (“RDF”). Mask datapreparation 1532 provides the RDF to mask fabrication 1544. Maskfabrication 1544 includes a mask writer. A mask writer converts the RDFto an image on a substrate, such as a mask (reticle) 1545 or asemiconductor wafer 1553. The IC design layout diagram 1522 ismanipulated by mask data preparation 1532 to comply with particularcharacteristics of the mask writer and/or requirements of IC fab 1550.In FIG. 15 , data preparation 1532 and mask fabrication 1544 areillustrated as separate elements. In some embodiments, data preparation1532 and mask fabrication 1544 can be collectively referred to as maskdata preparation.

In some embodiments, data preparation 1532 includes optical proximitycorrection (OPC) which uses lithography enhancement techniques tocompensate for image errors, such as those that can arise fromdiffraction, interference, other process effects and the like. OPCadjusts IC design layout diagram 1522. In some embodiments, datapreparation 1532 includes further resolution enhancement techniques(RET), such as off-axis illumination, sub-resolution assist features,phase-shifting masks, other suitable techniques, and the like orcombinations thereof. In some embodiments, inverse lithographytechnology (ILT) is also used, which treats OPC as an inverse imagingproblem.

In some embodiments, data preparation 1532 includes a mask rule checker(MRC) that checks the IC design layout diagram 1522 that has undergoneprocesses in OPC with a set of mask creation rules which contain certaingeometric and/or connectivity restrictions to ensure sufficient margins,to account for variability in semiconductor manufacturing processes, andthe like. In some embodiments, the MRC modifies the IC design layoutdiagram 1522 to compensate for limitations during mask fabrication 1544,which may undo part of the modifications performed by OPC in order tomeet mask creation rules.

In some embodiments, data preparation 1532 includes lithography processchecking (LPC) that simulates processing that will be implemented by ICfab 1550 to fabricate IC device 1560. LPC simulates this processingbased on IC design layout diagram 1522 to create a simulatedmanufactured device, such as IC device 1560. The processing parametersin LPC simulation can include parameters associated with variousprocesses of the IC manufacturing cycle, parameters associated withtools used for manufacturing the IC, and/or other aspects of themanufacturing process. LPC takes into account various factors, such asaerial image contrast, depth of focus (“DOF”), mask error enhancementfactor (“MEEF”), other suitable factors, and the like or combinationsthereof. In some embodiments, after a simulated manufactured device hasbeen created by LPC, if the simulated device is not close enough inshape to satisfy design rules, OPC and/or MRC are be repeated to furtherrefine IC design layout diagram 1522.

It should be understood that the above description of data preparation1532 has been simplified for the purposes of clarity. In someembodiments, data preparation 1532 includes additional features such asa logic operation (LOP) to modify the IC design layout diagram 1522according to manufacturing rules. Additionally, the processes applied toIC design layout diagram 1522 during data preparation 1532 may beexecuted in a variety of different orders.

After data preparation 1532 and during mask fabrication 1544, a mask1545 or a group of masks 1545 are fabricated based on the modified ICdesign layout diagram 1522. In some embodiments, mask fabrication 1544includes performing one or more lithographic exposures based on ICdesign layout diagram 1522. In some embodiments, an electron-beam(e-beam) or a mechanism of multiple e-beams is used to form a pattern ona mask (photomask or reticle) 1545 based on the modified IC designlayout diagram 1522. Mask 1545 can be formed in various technologies. Insome embodiments, mask 1545 is formed using binary technology. In someembodiments, a mask pattern includes opaque regions and transparentregions. A radiation beam, such as an ultraviolet (UV) beam, used toexpose the image sensitive material layer (for example, photoresist)which has been coated on a wafer, is blocked by the opaque region andtransmits through the transparent regions. In one example, a binary maskversion of mask 1545 includes a transparent substrate (for example,fused quartz) and an opaque material (for example, chromium) coated inthe opaque regions of the binary mask. In another example, mask 1545 isformed using a phase shift technology. In a phase shift mask (PSM)version of mask 1545, various features in the pattern formed on thephase shift mask are configured to have proper phase difference toenhance the resolution and imaging quality. In various examples, thephase shift mask can be attenuated PSM or alternating PSM. The mask(s)generated by mask fabrication 1544 is used in a variety of processes.For example, such a mask(s) is used in an ion implantation process toform various doped regions in semiconductor wafer 1553, in an etchingprocess to form various etching regions in semiconductor wafer 1553,and/or in other suitable processes.

IC fab 1550 includes wafer fabrication 1552. IC fab 1550 is an ICfabrication business that includes one or more manufacturing facilitiesfor the fabrication of a variety of different IC products. In someembodiments, IC Fab 1550 is a semiconductor foundry. For example, theremay be a manufacturing facility for the front end fabrication of aplurality of IC products (front-end-of-line (FEOL) fabrication), while asecond manufacturing facility may provide the back end fabrication forthe interconnection and packaging of the IC products (back-end-of-line(BEOL) fabrication), and a third manufacturing facility may provideother services for the foundry business.

IC fab 1550 uses mask(s) 1545 fabricated by mask house 1530 to fabricateIC device 1560. Thus, IC fab 1550 at least indirectly uses IC designlayout diagram 1522 to fabricate IC device 1560. In some embodiments,semiconductor wafer 1553 is fabricated by IC fab 1550 using mask(s) 1545to form IC device 1560. In some embodiments, the IC fabrication includesperforming one or more lithographic exposures based at least indirectlyon IC design layout diagram 1522. Semiconductor wafer 1553 includes asilicon substrate or other proper substrate having material layersformed thereon. Semiconductor wafer 1553 further includes one or more ofvarious doped regions, dielectric features, multilevel interconnects,and the like (formed at subsequent manufacturing steps).

As described above, integrated circuits in the present disclosureprovide extra conductive paths for transmitting signals in the gatestructures of multiple stages circuit. Therefore, the resistancegenerated by the routing between the gate structures is reduced, and thecircuit performance is accordingly improved.

In some embodiments, an integrated circuit is disclosed, including afirst gate and a second gate disposed in a first layer, and aligned witheach other in a first direction; a first gate via disposed on the firstgate and a second gate via disposed on the second gate; at least onefirst conductive segment and at least one second conductive segmentdisposed in a second layer above the first layer, in which the first andsecond conductive segments are coupled to the first and second gate viasrespectively; and a first conductive line disposed in a third layerabove the second layer and extending in the first direction; in whichthe first and second gates are configured to be a terminal of a firstlogic circuit, in which the first conductive line is electricallycoupled to the first gate through a first connection via, the firstconductive segment, and the first gate via, in which the firstconductive line is electrically coupled to the second gate through asecond connection via, the second conductive segment, and the secondgate via. In some embodiments, the first and second gates are connectedto each other as a gate structure extending in the first direction. Insome embodiments, the semiconductor structure further includes a firstactive area and a second active area separated from each other in thefirst direction and extending in a second direction different from thefirst direction; in which the at least one first gate via includesmultiple first gate vias, and the at least one second gate via includesmultiple second gate vias; in which a number of the first gate vias arealigned along a width of the first active area in the first direction,and a number of the second gate vias are aligned aling a width of thesecond active area in the first direction. In some embodiments, thenumber of the first gate vias increases as the width of the first activearea increases. In some embodiments, the at least one first gate via andthe at least one second gate via include multiple first gate vias andmultiple second gate vias, respectively; in which the number of thefirst gate vias and the number of the second gate vias are the same. Insome embodiments, the semiconductor structure further includes a firstactive area and a second active area separated from each other in thefirst direction extending in a second direction different from the firstdirection; in which the first gate via aligns with a center of the firstactive area in the first direction and the second gate via aligns with acenter of the second active area in the first direction. In someembodiments, the semiconductor structure further includes a third gateand a fourth gate disposed in the first layer, aligned with each otherin the first direction; a third gate via disposed on the third gate anda fourth gate via disposed on the fourth gate; a third conductivesegment coupled to the third gate and a fourth conductive segmentcoupled to the fourth gate, in which the third and fourth conductivesegments are disposed in the second layer; and a second conductive linedisposed in the third layer and extending in the first direction; inwhich the third and fourth gates are configured to be a terminal of asecond logic circuit, the first and second logic circuits coupled toeach other.

Also disclosed is an integrated circuit that includes a first pair oftransistors including a first gate extending along a first direction;and a first active area and a second active area separated from thefirst active area in the first direction, in which the first gatecrosses the first active area and the second active area; at least onefirst gate via and at least one second gate via that are coupled to thefirst gate, in which the at least one first gate via is arranged closerto the first active area than the at least one second gate via is; and afirst conductive line electrically coupled to the at least one firstgate via and the at least one second gate via; in which the at least onefirst gate via, the at least one second gate via, and the firstconductive line are included in a conductive path coupled to the firstof the first pair of transistors. In some embodiments, the at least onefirst gate via aligns with a center, in the first direction, of thefirst active area. In some embodiments, the at least one first gate viaand the at least one second gate via include multiple first gate viasand multiple second gate vias; in which a resistance of the conductivepath is associated with a number of the first gate vias and a number ofthe second gate vias. In some embodiments, a width of the first activearea is based on the number of the first gate vias. In some embodiments,the first gate includes: a first portion and a second portion separatedfrom the first portion in the first direction, in which the at least onefirst gate via is disposed on the first portion of the first gate, andthe at least one second gate via is disposed on the second portion ofthe first gate. In some embodiments, a ratio of a width of the firstconductive line over a width of the first portion of the first gate isfrom about 1 to about 20. In some embodiments, in which the at least onefirst gate via includes: multiple first gate vias, and a resistance ofthe conductive path increases in response to a number of the pluralityof first gate vias decreasing. In some embodiments, the number of thefirst gate vias varies as a width of the first active area varies. Insome embodiments, the integrated circuit further includes a second pairof transistors, including: a second gate of a first transistor of thesecond pair of transistors and a third gate of a second transistor ofthe second pair of transistors; in which the second gate crosses thefirst active area, and the third gate crosses the second active area; athird gate via disposed on the second gate; a fourth gate via disposedon the third gate; and a second conductive line electrically coupled tothe third gate via and the fourth gate via.

Also disclosed is a method including the following operations: forming agate structure shared by a first transistor of a first type and a secondtransistor of a second type different from the first type; forming atleast one first gate via and at least one second gate via on the gatestructure; and forming a conductive line coupled to the gate structurethrough a plurality of conductive vias, a plurality of conductivesegments, the at least one first gate via, and the at least one secondgate via; in which the gate structure and the conductive line extend ina first direction. In some embodiments, a ratio of a width of theconductive line to a width of the gate structure ranges from about 1 toabout 20, and in which a ratio of a height of the conductive line to aheight of the gate structure ranges from about 1 to about 40. In someembodiments, the method further includes forming a first active area ofthe first transistor and a second active area of the second transistorthat are separated from each other in the first direction and extendingin a second direction different from the first direction, in which theat least one first gate via aligns with a center of the first activearea in the first direction. In some embodiments, numbers of the atleast one first gate via and the at least one second gate via vary as alength of the gate structure varies.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A structure, comprising: a first gate and asecond gate; at least one first gate via disposed on the first gate andat least one second gate via disposed on the second gate, wherein the atleast one first gate via and the at least one second gate via comprise aplurality of first gate vias and a plurality of second gate vias,respectively, and wherein a number of the plurality of first gate viasand a number of the plurality of second gate vias are the same; a firstconductive segment and a second conductive segment connected to the atleast one first gate via; and a conductive line disposed above the firstconductive segment.
 2. The structure of claim 1, wherein the first andsecond gates are connected to each other.
 3. The structure of claim 2,further comprising a first active area and a second active areaseparated from each other, wherein the at least one first gate viacomprises a plurality of first gate vias aligned along a width of thefirst active area and the at least one second gate via comprises aplurality of second gate vias aligned along a width of the second activearea.
 4. The structure of claim 2, further comprising a first activearea and a second active area separated from each other, wherein the atleast one first gate via aligns with a center of the first active areain the first direction and the second gate via aligns with a center ofthe second active area.
 5. The structure of claim 1, wherein the atleast one first gate and the at least one second gate are configured tobe a terminal of a logic circuit.
 6. The structure of claim 1, furthercomprising: a third gate and a fourth gate aligned with each other; athird gate via disposed on the third gate and a fourth gate via disposedon the fourth gate; and a third conductive segment coupled to the thirdgate and a fourth conductive segment coupled to the fourth gate, whereinthe third and fourth gates are configured to be a terminal of an otherlogic circuit coupled to the logic circuit.
 7. The structure of claim 1,wherein the conductive line is disposed above the first conductivesegment.
 8. A structure, comprising: a first active area and a secondactive area; a gate disposed over the first active area and secondactive area; first gate vias and second gate vias coupled to the gate,wherein the first gate vias are arranged closer to the first active areathan the second gate vias; and a conductive segment connected to thefirst gate vias, wherein the first gate vias and the second gate viascomprise a different number of first gate vias and second gate vias,respectively.
 9. The structure of claim 8, wherein the first gate viasalign with a center of the first active area.
 10. The structure of claim8, further comprising a conductive line disposed above the conductivesegment and electrically coupled to the first gate vias and the secondgate vias.
 11. The structure of claim 10, wherein the gate comprises afirst portion and a second portion separated from each other, whereinthe first gate vias are disposed on the first portion and the secondgate vias are disposed on the second portion.
 12. The structure of claim11, wherein a ratio of width of the conductive line to a width of thefirst portion of the gate is about 1 to about
 20. 14. The structure ofclaim 8, wherein the first gate vias, the second gate vias, and theconductive line are included in a conductive path.
 13. The structure ofclaim 8, wherein a resistance of the conductive path increases inresponse to number of first gate vias decreasing.
 15. The structure ofclaim 8, further comprises a source/drain via electrically connected tothe conductive segment.
 16. The structure of claim 8, further comprisingan other gate disposed over the first active area.
 17. A method,comprising: forming a gate structure shared by a first transistor and asecond transistor; forming at least one first gate via and at least onesecond gate via on the gate structure; forming a first conductivesegment and a second conductive segment, wherein: the first conductivesegment is connected to the at least one gate via and at least one firstsource/drain via, the second conductive segment is connected to the atleast one second gate via and at least one second source/drain via, andthe first and second conductive segments are above the gate structure;and forming a conductive line above the first and second conductivesegments and coupled to the gate structure through a plurality ofconductive vias, a plurality of conductive segments, the at least onefirst gate via, and the at least one second gate via, wherein a ratio ofa width of the conductive line to a width of the gate structure rangesfrom about 1 to about
 20. 18. The method of claim 17, wherein a ratio ofa height of the conductive line to a height of the gate structure rangesfrom about 1 to about
 40. 19. The method of claim 17, furthercomprising: forming a first active area of the first transistor and asecond active area of the second transistor that are separated from eachother, wherein the at least one first gate via aligns with a center ofthe first active area.
 20. The method of claim 17, wherein a number ofthe at least one first gate via and a number of the at least one secondgate via vary as a length of the gate structure varies.